1. Field of the Invention
The present invention generally relates to methods and systems for data transfer.
2. Background Art
Conventionally, data transfers in computational devices are initiated and managed by an application running on a processor. These data transfers consume processor bandwidth. These data transfers also slow because bus arbitration over a congested system bus may have to be performed for each data transfer. Direct Memory Access (DMA) engines also use the system bus and are unable to overcome this deficiency. Furthermore, DMA engines are limited to data transfers between main memory and hard disk drives.
Furthermore, errors during data transfer may not be detected until the end of a data transfer when an error checking mechanism such as a cyclic redundancy check (CRC) is used. Furthermore mechanisms do no exist to detect real time patterns in data being transferred.
Methods and systems are needed to overcome the above mentioned deficiencies.
The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.